reset in p00 in p02/so/sbo i/o p03/si in p50 i/o p51 i/o p52 i/o p53 i/o p30 i/o p31 i/o p32 i/o p33 i/o p60 i/o p61 i/o p62 i/o p63 i/o p20 i/o p21 i/o p22/pcl i/o p23 i/o p10/int0 in p12/int2 in x2 in x1 in p01/ sck i/o v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 gnd input
int0
int2
p00, p03
p10, p12
reset
sck
s1
x1, x2
v pp
input/output
p01 - p02
p20 - p23
p30 - p33
p50 - p53
p60 - p63
sbo
pcl
so
: vector interrupt request for edge detect
: external test for edge detect
: 4-bit port (port 0)
: 2-bit port (port 1)
: system reset
: serial clock
: serial data
: system clock
: program supply voltage, (normal operation : gnd)
: 4-bit port (port 0)
: 4-bit port (port 2)
: programmable 4 bit port (port 3)
: 4-bit n-ch open drain port (port 5)
: 4-bit port (port 6)
: serial bus
: clock
: serial data 15 16 17 18 19 20 21 22 23 24 25 26 27 28 * 1 3
4
5
6
24
25
27
26
2 p00
p01/ sck
p02/so/sbo
p03/si
p10/int0
p12/int2
x1
x2
reset p20
p21
p22/pcl
p23
p30
p31
p32
p33
p50
p51
p52
p53
p60
p61
p62
p63 20
21
22
23
11
12
13
15
7
8
9
10
16
17
18
19 * 1
UPD750402A
upd75p402c
: nc
: v pp upd75402a (1/2)
ild c-mos 4-bit single chip micro computers
?op view
upd75402a (2/2) program
counter (11) rom
program
memory
1920 x 8bit decode
and
control clock
output
control fxx/2 n 22 27 26 pcl x1 x2 (fxx = 4.19 mh z ) cpu clock
( ) clock
divider clock
generator stand by
control alu cy sp general reg. ram
data memory
64 x 4-bit basic
interval
timer intbt intcsi 6 5 4 24 25 si so/sbo sck int 0 int 2 serial
interface port 0 port 1 port 2 port 3 port 5 port 6 3 - 6 4 2 4 4 4 4 24, 25 20 - 23 11 - 13, 15 7 - 10 16 - 19 p00 - p03 p10, p12 p20 - p23 p30 - p33 p50 - p53 p60 - p63 interrupt
control 28 v dd 14 gnd 2 reset 1 v pp (upd75p402c)
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